(1) Field of the Invention
The invention pertains generally to digital communication, in particular to digital signal processing and signal detection in the presence of noise, particularly using matched filters.
(2) Description of Prior Art
Several basic and often conflicting problems in signal detection are maximizing the signal to noise ratio of the detection process, minimizing the amount of engineering resources necessary for detection, and maximizing the speed of detection. A standard approach, if one has a priori knowledge of an incoming signal, is to detect the signal by correlating it with a matched filter, i.e., a filter whose impulse response is the time reversed complex conjugate of the expected signal. Moreover, if one has a priori knowledge of signal phase, one can further increase signal to noise ratio by sampling the signal at the Nyquist rate and only in the frequency domain vicinity of expected signal peaks. If, on the other hand, one has no prior knowledge of signal phase, one must asynchronously (incoherently) oversample the signal at higher than the Nyquist rate to increase the likelihood of sampling at or near optimum phase, i.e., at or near peaks. This type of sampling requires more computing power, more sample bits and larger sample bit sizes, and more programmable logic blocks to implement the shift registers needed for real time correlation of incoming signals with reference signals. If one wishes to compare an incoming signal with a number of reference signals, one must perform the comparison serially with each of the several reference signals, an inherently slow process if one uses only one register for the incoming signal. Conversely, if one feeds the incoming signal in parallel to plural registers each associated with one reference signal, the process is faster but at the cost of significantly more dedicated registers and logic blocks.
A device commonly used in digital signal processing is the Field-Programmable Gate Array (FPGA), which is an integrated circuit containing large arrays of configurable logic blocks and dedicated random access memory blocks. A configurable logic block typically contains programmable look-up tables that can implement low-level combinational logic. Configurable logic blocks are connectable to one another and can effect extremely complex combinational logic functions such as shift registers, state machines, and even microprocessors. FPGAs are easily reconfigurable and reprogrammable as desired, thus making them ideal for development applications.